Embedded processing system with multi-stage authentication

ABSTRACT

An embedded processing system includes processing circuitry configured to execute a plurality of computer executable instructions. The embedded processing system also includes a memory system configured to store a plurality of configuration items, where at least one of the configuration items includes a sequence of the computer executable instructions. The embedded processing system also includes an authentication control configured to authenticate an immutable anchor associated with the embedded processing system, authenticate integrity of a reconfigurable entity map associated with the memory system, authenticate the configuration items based on the reconfigurable entity map, and perform an accommodation measure based on an authentication failure of at least one of the configuration items.

BACKGROUND

The subject matter disclosed herein generally relates to embedded processing systems and, more particularly, to a method and an apparatus for multi-stage authentication for an embedded processing system.

Embedded processing systems can include control system software that is critical to the physical performance of a control system. For example, a vehicle control system relies on a combination of carefully crafted control processes using a combination of instructions, constant data, and dynamically adjusted data to operate one or more electromechanical systems. If configuration items, such as software and/or data are modified, whether intentionally or unintentionally, the control system may be at risk of exhibiting undesirable behavior and/or degraded performance.

BRIEF DESCRIPTION

According to one embodiment, an embedded processing system includes processing circuitry configured to execute a plurality of computer executable instructions. The embedded processing system also includes a memory system configured to store a plurality of configuration items, where at least one of the configuration items includes a sequence of the computer executable instructions. The embedded processing system also includes an authentication control configured to authenticate an immutable anchor associated with the embedded processing system, authenticate integrity of a reconfigurable entity map associated with the memory system, authenticate the configuration items based on the reconfigurable entity map, and perform an accommodation measure based on an authentication failure of at least one of the configuration items.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the immutable anchor is hardware or software that establishes a root and chain of trust in authentication.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the reconfigurable entity map defines a list of address ranges for authenticating the configuration items in the memory system.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the list of address ranges includes two or more address ranges for one of the configuration items.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where two or more different accommodation measures are defined for the list of address ranges.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the reconfigurable entity map identifies at least one of the address ranges to skip authentication.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the accommodation measure includes one or more of: resetting the embedded processing system, switching the embedded processing system to a fail-safe mode of operation, and transmitting an authentication failure message on a communication interface.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where authentication includes one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where one or more of the configuration items are decrypted prior to authentication within the embedded processing system.

In addition to one or more of the features described above or below, or as an alternative, further embodiments may include where the embedded processing system is a controller of a gas turbine engine, and at least one of the configuration items includes an application configured to control operation of the gas turbine engine.

According to an embodiment, an authentication control of an embedded processing system authenticates an immutable anchor associated with the embedded processing system and can establish a root of trust. The authentication control authenticates integrity of a reconfigurable entity map associated with a memory system of the embedded processing system. The authentication control authenticates a plurality of configuration items in the memory system based on the reconfigurable entity map. An accommodation measure is performed based on an authentication failure of at least one of the configuration items.

A technical effect of the apparatus, systems and methods is achieved by multi-stage authentication for an embedded processing system as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The following descriptions should not be considered limiting in any way. With reference to the accompanying drawings, like elements are numbered alike:

FIG. 1 is a block diagram of a system, in accordance with an embodiment of the disclosure;

FIG. 2 is a block diagram of a plurality of configuration items for authentication, in accordance with an embodiment of the disclosure;

FIG. 3 is a block diagram of an authentication process, in accordance with an embodiment of the disclosure; and

FIG. 4 is a flow chart illustrating a method, in accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

A detailed description of one or more embodiments of the disclosed apparatus and method are presented herein by way of exemplification and not limitation with reference to the Figures.

Referring now to the drawings, FIG. 1 illustrates a system 100 that includes an embedded processing system 102 and a controlled system 104. The controlled system 104 can be any type of physical system that includes one or more effectors 106 controlled by one or more effector commands 108 generated by the embedded processing system 102. Examples of effectors 106 can include one or more motors, solenoids, valves, relays, pumps, heaters, and/or other such actuation control components. A plurality of sensors 110 can capture state data associated with the controlled system 104 and provide sensed values 112 as feedback to the embedded processing system 102 to enable closed-loop control of the controlled system 104 according to one or more control laws. Examples of the sensors 110 can include one or more temperature sensors, pressure sensors, strain gauges, level sensors, accelerometers, rate sensors, and the like. The controlled system 104 can be an engine, a vehicle, a heating, ventilating, and air conditioning (HVAC) system, an elevator system, industrial machinery, or the like. For purposes of explanation, embodiments are primarily described with respect to an engine system of an aircraft as the controlled system 104, such as a gas turbine engine, where the embedded processing system 102 may provide one or more control channels and/or monitoring systems of a controller (e.g., a full authority digital engine control) of one or more gas turbine engines.

In the example of FIG. 1, the embedded processing system 102 includes processing circuitry 114 and a memory system 116 configured to store a plurality of configuration items, where at least one of the configuration items includes a sequence of the computer executable instructions for execution by the processing circuitry 114. The executable instructions may be stored or organized in any manner and at any level of abstraction, such as in connection with controlling and/or monitoring operation of the controlled system 104. The processing circuitry 114 can be any type or combination of central processing unit (CPU), including one or more of: a microprocessor, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Also, in embodiments, the memory system 116 may include volatile memory 118, such as random access memory (RAM), and non-volatile memory 120, such as Flash memory, read only memory (ROM), and/or other electronic, optical, magnetic, or any other computer readable medium onto which is stored data and algorithms in a non-transitory form.

The embedded processing system 102 can also include one or more of an input/output interface 122, a communication interface 124, an authentication control 126, and/or other elements (not depicted). The input/output interface 122 can include support circuitry for interfacing with the effectors 106 and sensors 110, such as filters, amplifiers, digital-to-analog converters, analog-to-digital converters, and other such circuits to support digital and/or analog interfaces. Further, the input/output interface 122 can receive or output signals to/from other sources. As one example, discrete inputs 128 can be input to the input/output interface 122 to establish an operating mode of the embedded processing system 102 or to trigger actions by the embedded processing system 102. A reset signal 130 may also be received as a signal by the input/output interface 122 or may interface with other circuitry of the embedded processing system 102, such as power conditioning circuitry (not depicted). The communication interface 124 can be communicatively coupled to a communication system 132, which can include one or more direct or networked communication links to systems, such as a loader system 134, a data repository 136, or another system (not depicted). The loader system 134 can be any type of computer system operable to load new/updated configuration items to the embedded processing system 102 for storage in the memory system 116. The loader system 134 can interface to the communication system 132 through a wired, wireless, optical, or magnetic coupling. The data repository 136 can serve as a data source for updating the memory system 116, for instance, with control system data, or as a data sink to offload and clear data from the memory system 116, such as fault data, history data, and the like.

In embodiments, the authentication control 126 can be implemented in dedicated circuitry, such as an application specific integrated circuit, programmable logic device, field programmable gate array, or the like. Alternatively, the authentication control 126 can be implemented in software, such as boot software. In some embodiments, a processing core of the processing circuitry 114 can be dedicated for use by the authentication control 126. The authentication control 126 can be configured to implement embodiments as further described herein.

Referring now to FIG. 2, an example of a plurality of configuration items 200 for authentication is depicted. The configuration items 200 of FIG. 2 can include one or more of a boot control 210, a reconfigurable entity map 212, an operating system 214, an application 216, constant data 218, and/or configurable data 220. Further, there can be multiple instances of the configuration items 200, such as multiple instances of the application 216, constant data 218, configurable data 220, and/or other items. The configuration items 200 can have different levels of criticality and authentication required. The boot control 210 can manage the loading and/or initialization of other configuration items 200. The reconfigurable entity map 212 can define address ranges and authentication requirements of the configuration items 200. The operating system 214 can provide scheduling and support for one or more applications 216 to interface with various hardware elements of the embedded control system 102 of FIG. 1. One or more applications 216 that use constant data 218 and/or configurable data 220 can be invoked by the operating system 214. The application 216 can be, for example, configured to control operation of the controlled system 104 of FIG. 1.

FIG. 3 depicts an example of an authentication process 300 that can be performed by the authentication control 126 of FIG. 1. Upon receiving a reset signal 130, a root authentication 302 authenticates an immutable anchor 304. The immutable anchor 304 is hardware or software that establishes a root and chain of trust in authentication. As one example, the immutable anchor 304 can be encoded in a read-only register that is accessible by the authentication control 126. Authentication of the immutable anchor 304 can include use of key pairs, certificates, signatures, and/or other known authentication techniques. Upon successful authentication 306 of the immutable anchor 304 during root authentication 302, the authentication control 126 can perform entity map authentication 308 of the reconfigurable entity map 212. Authentication can include one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure. For instance, if an incorrect key was used to sign the software, the corresponding key pair does not exist in the embedded processing system 102, or the software was tampered with, an authentication result may be a failure of a signature to authenticate. As a further example, an authentication failure can be detected for a memory range defined in the reconfigurable entity map 212 due to tampering of the memory content in the address range when the correct key exists.

Upon successful authentication 310 of the reconfigurable entity map 212 during entity map authentication 308, the contents of the reconfigurable entity map 212 can be used to locate a plurality of configuration items 312, which may be embodiments of the plurality of configuration items 200 of FIG. 2, including a first configuration item 312A up to configuration item 312N, where N represents any number of configuration items 312. In embodiments, the entity map authentication 308 defines a list of address ranges for authenticating the configuration items 312 in the memory system 116 of FIG. 1. Reconfigurable address ranges provide flexibility in authentication boundaries. Each of the configuration items 312 can be a sequence of executable instructions (e.g., executable by the processing circuitry 114) or data values, such as values that support execution of instructions (e.g., constant or trim values). Address ranges in the entity map authentication 308 may have a one-to-one correspondence with one or more of the configuration items 312, or the list of address ranges can include two or more address ranges for at least one of the configuration items 312. For example, an address range can identify a location and size of the first configuration item 312A in the memory system 116 as a single item for authentication 314. Further, multiple address ranges 316A, 316B, 316C, 316N can be associated with a single configuration item, such as configuration item 312N. Thus, rather than performing a single authentication for configuration item 312N, each of the address ranges 316A, 316B, 316C, 316N can have a corresponding authentication 318A, 318B, 318C, 318N.

The authentications 314, 318A-318N may also have different accommodation measures to handle authentication failure conditions. For example, different levels of criticality may be assigned to each of the configuration items 312 and/or address ranges 316A-316N. A high level of criticality may be assigned to instructions or control parameters for the controlled system 104, where degraded/faulty performance or non-performance of control operations could occur if non-authenticated instructions or control parameters are used. If the configuration items 312 are partitioned to include instruction sequences that are not critical to operation of the controlled system 104, such as diagnostic code, a lower level of criticality can be assigned that may not impede normal operation of controlling the controlled system 104. Further, the reconfigurable entity map can identify at least one of the address ranges 316A-31N to skip authentication, for instance, when a range of memory has to be authenticated during a software load, i.e., reprogramming of the embedded processing system 102, but not when the embedded processing system 102 powers up to control the controlled system 104.

Referring now to FIG. 4 with continued reference to FIGS. 1-3, FIG. 4 is a flow chart illustrating a method 400 for multi-step authentication, in accordance with an embodiment. The method 400 may be performed, for example, by the authentication control 126 of FIG. 1.

At block 402, the authentication control 126 can authenticate an immutable anchor 304 associated with the embedded processing system 102 as part of root authentication 302. At block 404, the authentication control 126 can authenticate integrity of a reconfigurable entity map 212 associated with the memory system 116 of the embedded processing system 102 as part of entity map authentication 308. At block 406, the authentication control 126 can authenticate the configuration items 200, 312 based on the reconfigurable entity map 212. The embedded processing system 102 can perform an accommodation measure based on an authentication failure of at least one of the configuration items 200, 312. The accommodation measure can include one or more of: resetting the embedded processing system 102, switching the embedded processing system 102 to a fail-safe mode of operation, and/or transmitting an authentication failure message on a communication interface 124 to the communication system 132. The accommodation measure may be selected based on a level of criticality associated with the item being authenticated, where the level of criticality may be fixed or assigned based on one or more values of the reconfigurable entity map 212. For example, two or more different accommodation measures can be defined for a list of address ranges in the reconfigurable entity map 212. Failure accommodation for authentication failures may not be deferred after all entities are authenticated. Accommodation may happen immediately following a failure depending on the criticality of the function performed by the configuration item. For example, authentication failure of the immutable anchor can be immediate, but failure accommodation for a configuration item that does some diagnostic functionality may be simply to log a fault, and disable execution of the function.

In embodiments, one or more of the configuration items 200, 312, can be decrypted prior to authentication within the embedded processing system 102. For example, when one or more of the configuration items 200, 312 are provide from the loader system 134, data repository 136, and/or other source, the configuration items 200, 312 can be in an encrypted format and written temporarily into the volatile memory 118 for authentication prior to updating intended storage addresses within the non-volatile memory 120. The one or more of the configuration items 200, 312 can be signed and encrypted at a point of generation and encrypted and signed again for transfer to the loader system 134. The loader system 134 can decrypt the one or more of the configuration items 200, 312 and verify one or more associated signatures before transfer to the embedded processing system 102. Within the embedded processing system 102, the one or more of the configuration items 200, 312 can be decrypted and one or more associated signatures verified, for instance, during transfer into non-volatile memory 120 in the embedded processing system 102. The authentication control 126 may work in conjunction with the boot control 210 to manage the loading, authentication, and storage of the configuration items 200, 312 in the memory system 116. The boot control 210 can send a response indicating a success or failure of signature verification and/or authentication to the loader system 134. Upon successful authentication, a decrypted version of the one or more of the configuration items 200, 312 can be written to the non-volatile memory 120. As an alternative, one or more of the configuration items 200, 312 can be stored in the non-volatile memory 120 in an encrypted format and be decrypted and transferred to the volatile memory 118 upon authentication during a start-up process. If updates are made to the one or more of the configuration items 200, 312 in the volatile memory 118, periodic backup copies may be written to the non-volatile memory 120 (in an encrypted or decrypted format) to support recovery operations due to a loss of power or assertion of the reset signal 130.

While the above description has described the flow process of FIG. 4 in a particular order, it should be appreciated that unless otherwise specifically required in the attached claims that the ordering of the steps may be varied.

The term “about” is intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

While the present disclosure has been described with reference to an exemplary embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the essential scope thereof. Therefore, it is intended that the present disclosure not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this present disclosure, but that the present disclosure will include all embodiments falling within the scope of the claims. 

What is claimed is:
 1. An embedded processing system comprising: processing circuitry configured to execute a plurality of computer executable instructions; a memory system configured to store a plurality of configuration items, wherein at least one of the configuration items comprises a sequence of the computer executable instructions; and an authentication control configured to: authenticate an immutable anchor associated with the embedded processing system; authenticate integrity of a reconfigurable entity map associated with the memory system of the embedded processing system; authenticate the configuration items based on the reconfigurable entity map; and perform an accommodation measure based on an authentication failure of at least one of the configuration items.
 2. The embedded processing system of claim 1, wherein the immutable anchor is hardware or software that establishes a root and chain of trust in authentication.
 3. The embedded processing system of claim 1, wherein the reconfigurable entity map defines a list of address ranges for authenticating the configuration items in the memory system.
 4. The embedded processing system of claim 3, wherein the list of address ranges comprises two or more address ranges for one of the configuration items.
 5. The embedded processing system of claim 3, wherein two or more different accommodation measures are defined for the list of address ranges.
 6. The embedded processing system of claim 3, wherein the reconfigurable entity map identifies at least one of the address ranges to skip authentication.
 7. The embedded processing system of claim 1, wherein the accommodation measure comprises one or more of: resetting the embedded processing system, switching the embedded processing system to a fail-safe mode of operation, and transmitting an authentication failure message on a communication interface.
 8. The embedded processing system of claim 1, wherein authentication comprises one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure.
 9. The embedded processing system of claim 1, wherein one or more of the configuration items are decrypted prior to authentication within the embedded processing system.
 10. The embedded processing system of claim 1, wherein the embedded processing system is a controller of a gas turbine engine, and at least one of the configuration items comprises an application configured to control operation of the gas turbine engine.
 11. A method comprising: authenticating, by an authentication control of an embedded processing system, an immutable anchor associated with the embedded processing system; authenticating, by the authentication control, integrity of a reconfigurable entity map associated with a memory system of the embedded processing system; authenticating, by the authentication control, a plurality of configuration items in the memory system based on the reconfigurable entity map; and performing an accommodation measure based on an authentication failure of at least one of the configuration items.
 12. The method of claim 11, wherein the immutable anchor is hardware or software that establishes a root and chain of trust in authentication.
 13. The method of claim 11, wherein the reconfigurable entity map defines a list of address ranges for authenticating the configuration items in the memory system.
 14. The method of claim 13, wherein the list of address ranges comprises two or more address ranges for one of the configuration items.
 15. The method of claim 13, wherein two or more different accommodation measures are defined for the list of address ranges.
 16. The method of claim 13, wherein the reconfigurable entity map identifies at least one of the address ranges to skip authentication.
 17. The method of claim 11, wherein the accommodation measure comprises one or more of: resetting the embedded processing system, switching the embedded processing system to a fail-safe mode of operation, and transmitting an authentication failure message on a communication interface.
 18. The method of claim 11, wherein authentication comprises one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure.
 19. The method of claim 11, wherein one or more of the configuration items are decrypted prior to authentication within the embedded processing system.
 20. The method of claim 11, wherein the embedded processing system is a controller of a gas turbine engine, and at least one of the configuration items comprises an application configured to control operation of the gas turbine engine. 